In the field of semiconductor device manufacturing, many factors may affect the performance of a semiconductor device such as, for example, a field-effect-transistor (FET). For example, channel width of a FET may affect the total amount of electronic current that the FET is able to deliver or provide during operation. In reality, for various performance requirements, manufacturing of FETs of variable channel widths is often required or desirable, sometimes on a single chip and sometimes in a densely populated area to be placed next to each other, in order to fulfill particular combination of performances of the devices under manufacturing.
In a planar field-effect-transistor, changes of channel width are often accomplished by simply forming gate structures over substrate areas of different widths which ultimately become the channel widths of the devices. With recent advancement in semiconductor device manufacturing, fin-type field-effect-transistors (FinFETs) are becoming increasingly popular and common because of their advanced performance and ability of achieving high device density. Nevertheless, based upon current technology, channel widths of FinFETs are generally discretized. In other words, unlike a planar FET, widths of the fins over which gate structures of the FinFETs are normally formed are only allowed to have a limited number of different widths according to existing ground rules, which significantly limits the choices of design of devices, such as a static random access memory (SRAM) that may be manufactured. This is because designability, or choice of design, of a SRAM for example is at least partially based upon the ability of adjustment to the device width of different transistors used, such as pass gate (PG), pull-up (PU) and pull-down (PD) transistors.